1. Field of the Invention
The present invention relates to semiconductor packages, and, more particularly, to a semiconductor package having an enhanced structure strength and a method of manufacturing the same.
2. Description of Related Art
With the flourishing of electronic industry, electronic products are gradually having various functions and high performance. In order to meet the package requirement for the miniaturization of semiconductor packages, a wafer level packaging (WLP) technique is thus developed. However, with the advance of technology, an electronic package structure is required to be provided with more input/output (I/O) in order to have its performance improved, and meet the requirements for electronic package products in the future. Therefore, the technique of having trace layout on both sides of a semiconductor is developed to meet the number requirement of I/O of a package product.
FIGS. 1A-1E are cross-sectional views of a method for manufacturing a semiconductor package 1 according to the prior art.
As shown in FIG. 1A, a mold 13 is provided, a carrier 10 having a connection layer 100 is disposed at top and bottom sides of the mold 13, the connection layer 100 has a plurality of first semiconductor elements 11 and second semiconductor elements 14 disposed thereon, and an encapsulant 12 is filled in the mold 13.
As shown in FIG. 1B, the mold 13 is compressed such that the encapsulant 12 encapsulates the first semiconductor elements 11 and second semiconductors 14. Subsequently, the mold 13, the carrier 10 and the connection layer 100 thereof are removed to obtain a package unit 1a. 
As shown in FIG. 1C, which illustrates a portion of FIG. 1B, a plurality of perforations 160 penetrating the encapsulant 12 are formed.
As shown in FIG. 1D, conductors 16 are formed in the perforations 160.
As shown in FIG. 1E, redistribution layer structures 17 are formed on the top and bottom sides of the encapsulant 12, such that the redistribution layer structures 17 are electrically connected to the conductors 16 and the first and second semiconductor elements 11 and 14. Subsequently, conductive elements 19 such as solder balls are formed on the bottom sides of the redistribution layer structures 17, such that the conductive element 19 is electrically connected to the redistribution layer structures 17 and external elements (not illustrated). A singularizing process is then performed to obtain a plurality of semiconductor packages 1.
However, after the mold 13, the carrier 10 and the connection layer 100 thereof are removed according to the prior art, the package unit 1a lacks sufficient support and protection, and thus is easily damaged while the perforations 160 are formed.
Moreover, due to lack of sufficient support and protection, warpage of the encapsulant 12 tends to occur. Therefore, the positioning of perforations 160 is easily shifted, such that the redistribution layer structures 17 are not effectively coupled to the conductors 16. It thus result in adverse influence on the electrical connection between the redistribution layer structures 17 and the conductors 16, and causing the poor yield, bad product reliability, and high cost.
Thus, how to overcome various problems in the prior art is substantially an issue desired to be solved.